The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure that includes silicon germanium alloy fins located directly on a topmost surface of an oxide, and a method of forming the same.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In order to extend these devices for multiple technology nodes, there is a need to boost the performance with high-mobility channels.
A silicon germanium alloy (i.e., SiGe) is one promising channel material because of its high-carrier mobility. SiGe fins can be formed by epitaxially growing a SiGe alloy layer on a surface of a silicon (Si) substrate and then patterning the SiGe alloy layer. This prior art method of forming SiGe fins has some drawbacks associated therewith. For example, the direct epitaxial growth of SiGe on a Si substrate has a critical thickness limit. Above the critical thickness, SiGe is very defective and is not suitable for use as a device channel material. This prevents a thick SiGe layer for high fin height. Moreover, SiGe fins formed on a bulk Si substrate show a punch-though below the channel region. Furthermore, for current 7 nm technology, two sidewall image transfer (SIT) processes are needed to pattern fins having a 40 nm pitch. As such, process complexity is increased for current 7 nm technology due to the required need to use two SIT processes.
In view of the above, there is a need for providing a method of forming SiGe fins that avoids the drawbacks associated with prior art SiGe fin formation.